A conventional buried bit line ROM device 10 is illustrated in FIG. 1. Consider the case where the substrate 12 is P-type silicon. A plurality of spaced apart N.sup.+ -type bit lines 14 are diffused into the substrate. A plurality of spaced apart polysilicon word lines 16 are formed on top of the substrate. A single ROM cell is designated 18 in FIG. 1. Each individual ROM cell 18 has a source and drain regions 19, 20 formed by portions 21 and 22 of two adjacent bit lines. The channel L between the sourced and drain regions 20, 21 is located under the polysilicon word line 16. Prior to the formation of the polysilicon word line, the cell may be permanently placed in the off state or on state by the ion implantation of P-type or N-type impurities respectively.
A buried bit line Read Only Memory device of this type is discussed in detail in Mikiro Okada et al, "16 Mb ROM Design Using Bank Select Architecture," Integrated Circuits Group, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 532 Japan.
The cell size in a direction perpendicular to the word line direction is determined by the poly pitch (polysilicon word line plus spacing between lines).
It is an object of the present invention to increase the density of cells in a buried bit line ROM by decreasing the poly pitch of the word lines.